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Windows Memory Management
(Written by: Pankaj Garg)

1. Introduction
Windows on 32 bit x86 systems can access up to 4GB of physical memory. This is due to the fact
that the processor’s address bus which is 32 lines or 32 bits can only access address range from
0x00000000 to 0xFFFFFFFF which is 4GB. Windows also allows each process to have its own
4GB logical address space. The lower 2GB of this address space is available for the user mode
process and upper 2GB is reserved for Windows Kernel mode code. How does Windows give 4GB
address space each to multiple processes when the total memory it can access is also limited to
4GB. To achieve this Windows uses a feature of x86 processor (386 and above) known as paging.
Paging allows the software to use a different memory address (known as logical address) than the
physical memory address. The Processor’s paging unit translates this logical address to the physical
address transparently. This allows every process in the system to have its own 4GB logical address
space. To understand this in more details, let us first take a look at how the paging in x86 works.

2. Paging in x86 Processor
The x86 processor divides the physical address space (or physical memory) in 4 KB pages. Thus to
address 4GB of memory, we will need 1 Mega (1024x1024) 4KB pages. The processor uses a two
level structure to refer to these 1 Mega pages. You can think of it as a two dimensional matrix of
1024x1024 elements. The first dimension is known as Page Directory and second dimension is
known as Page Table. Thus we can create 1 Page directory with 1024 entries, each of which points
to a Page Table. This will allow us to have 1024 page tables. Each page table in turn can have 1024
entries, each of which points to a 4 KB page. Graphically it looks something like:

Page Directory

Page Tables

Physical Address

Index = 0, Address = X

Index = 0, Address = X1
Index = 1, Address = X2
Index = 2, Address = X3
…
Index = 1023, Address = Xn

Index = 1, Address = Y

Index = 0, Address = Y1
Index = 1, Address = Y2
Index = 2, Address = Y3
…
Index = 1023, Address = Yn
…
…
Index = 0, Address = Z1
Index = 1, Address = Z2
Index = 2, Address = Z3
…
Index = 1023, Address = Zn

Address X1 – 4 KB Page
Address Yn – 4 KB Page
Address X3 – 4 KB Page
Unused
Address Xn – 4 KB Page
Unused
Address Y1 – 4KB Page
Address X2 – 4KB Page
Address Z2 – 4KB Page
Address Y2 – 4KB Page
Address Z3 – 4KB Page
Unused
Unused
Address Zn –...
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Page 1 of 5
Windows Memory Management
(Written by: Pankaj Garg)
1. Introduction
Windows on 32 bit x86 systems can access up to 4GB of physical memory. This is due to the fact
that the processors address bus which is 32 lines or 32 bits can only access address range from
0x00000000 to 0xFFFFFFFF which is 4GB. Windows also allows each process to have its own
4GB logical address space. The lower 2GB of this address space is available for the user mode
process and upper 2GB is reserved for Windows Kernel mode code. How does Windows give 4GB
address space each to multiple processes when the total memory it can access is also limited to
4GB. To achieve this Windows uses a feature of x86 processor (386 and above) known as paging.
Paging allows the software to use a different memory address (known as logical address) than the
physical memory address. The Processors paging unit translates this logical address to the physical
address transparently. This allows every process in the system to have its own 4GB logical address
space. To understand this in more details, let us first take a look at how the paging in x86 works.
2. Paging in x86 Processor
The x86 processor divides the physical address space (or physical memory) in 4 KB pages. Thus to
address 4GB of memory, we will need 1 Mega (1024x1024) 4KB pages. The processor uses a two
level structure to refer to these 1 Mega pages. You can think of it as a two dimensional matrix of
1024x1024 elements. The first dimension is known as Page Directory and second dimension is
known as Page Table. Thus we can create 1 Page directory with 1024 entries, each of which points
to a Page Table. This will allow us to have 1024 page tables. Each page table in turn can have 1024
entries, each of which points to a 4 KB page. Graphically it looks something like:
Page Directory Page Tables
Index = 0, Address = X
Index = 0, Address = X1
Index = 1, Address = X2
Index = 2, Address = X3
Index = 1023, Address = Xn
Index = 1, Address = Y
Index = 0, Address = Y1
Index = 1, Address = Y2
Index = 2, Address = Y3
Index = 1023, Address = Yn
Index = 1023, Address = Z
Index = 0, Address = Z1
Index = 1, Address = Z2
Index = 2, Address = Z3
Index = 1023, Address = Zn
Physical Address
Address X1 4 KB Page
Address Yn 4 KB Page
Address X3 4 KB Page
Unused
Address Xn 4 KB Page
Unused
Address Y1 4KB Page
Address X2 4KB Page
Address Z2 4KB Page
Address Y2 4KB Page
Address Z3 4KB Page
Unused
Unused
Address Zn 4KB Page
Address Y3 4KB Page
Address Z1 4KB Page
Unused
Unused
so on
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