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The 8051 Microcontroller Address Decoding

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The 8051 Microcontroller
Address Decoding

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Ref. I. Scott Mackenzie, The 8051 Microcontroller

Address Decoding
• Address decoding is the process of generating chip select (CS) signals
from the address bus for each device in the system.
• The address bus lines are split into two sections:
• The N most significant bits are used to generate the CS signals for
different devices.
• The M least significant bits are passed to the devices as addresses
to the different memory cells.

Ref. I. Scott Mackenzie

sites.google.com/site/chithong

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An Example
• Let’s assume a simple microprocessor with 10 address lines.
• Let’s assume we wish to implement 1 KB memory using 128x8 memory
chips.
• Solution:
• We will need 8 memory chips (8 x 128 bytes = 1 KB).
• We will need 3 address lines to select each one of the 8 chips.
• Each chip will need 7 address lines to address its internal memory cells.

Ref. I. Scott Mackenzie

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Address Decoding Methods
• The previous example specified that all addressable memory space
was to be implemented but there are some situations where this
requirement is not necessary.
• If only a portion of the addressable space is going to be implemented
there are two basic address decoding strategies.
• Full address decoding:
• All the address lines are used to specify a memory location.
• Each physical memory location is identified by a unique address.
• Partial address decoding:
• Since not all the address space is implemented, only a subset of the
address lines are needed to point to the physical memory locations.
• Each physical memory location is identified by several possible
addresses.
Ref. I. Scott Mackenzie

sites.google.com/site/chithong

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Full Address Decoding
• Let’s assume the same microprocessor with 10 address lines (1 KB memory).
• Let’s assume we wish to implement 512 bytes memory using 128x8 memory
chips.

Ref. I. Scott Mackenzie

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5

Partial Address Decoding
• Let’s assume the same microprocessor with 10 address lines (1 KB memory).
• Let’s assume we wish to implement 512 bytes memory using 128x8 memory
chips. (Same requirements as the previous slide)

Ref. I. Scott Mackenzie

sites.google.com/site/chithong

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Implementing Address Decoders
• Logic gates (such as ANDs, ORs, NANDs, NORs, …)
• Decod...
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sites.google.com/site/chithong 1
Address Decoding
The 8051 Microcontroller
Lê Chí Thông
Ref. I. Scott Mackenzie, The 8051 Microcontroller
Address Decoding
Address decoding is the process of generating chip select (CS) signals
from the address bus for each device in the system.
The address bus lines are split into two sections:
The N most significant bits are used to generate the CS signals for
different devices.
The M least significant bits are passed to the devices as addresses
to the different memory cells.
Ref. I. Scott Mackenzie 2Lê Chí Thông
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