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Write testbench using System Verilog

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Writing Testbenches
using SystemVerilog

____________________________

Writing Testbenches
using SystemVerilog

by
Janick Bergeron
Synopsys, Inc.

13

Janick Bergeron
Verificationguild.com

Writing Testbenches Using SystemVerilog

Library of Congress Control Number: 2005938214
ISBN-10: 0-387-29221-7
ISBN-13: 9780387292212

ISBN-10: 0-387-31275-7 (e-book)
ISBN-13: 9780387312750 (e-book)

Printed on acid-free paper.
¤ 2006 Springer Science+Business Media, Inc.
All rights reserved. This work may not be translated or copied in whole or in part without
the written permission of the publisher (Springer Science+Business Media, Inc., 233 Spring
Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or
scholarly analysis. Use in connection with any form of information storage and retrieval,
electronic adaptation, computer software, or by similar or dissimilar methodology now
known or hereafter developed is forbidden.
The use in this publication of trade names, trademarks, service marks and similar terms,
even if they are not identified as such, is not to be taken as an expression of opinion as to
whether or not they are subject to proprietary rights.
Printed in the United States of America.
9 8 7 6 5 4 3 2 1
springer.com

TABLE OF CONTENTS

About the Cover
Preface

xiii
xv

Why This Book Is Important . . . . . . . . . . . . . . . . . . . xvi
What This Book Is About . . . . . . . . . . . . . . . . . . . . . xvi
What Prior Knowledge You Should Have . . . . . . . . xviii
Reading Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii
Why SystemVerilog? . . . . . . . . . . . . . . . . . . . . . . . . . xix
VHDL and Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . .xix
Hardware Verification Languages . . . . . . . . . . . . . . . . xx

Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
For More Information . . . . . . . . . . . . . . . . . . . . . . . xxii
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . xxii

CHAPTER 1

What is Verification?
What is a Testbench? . . . . . . . . . . . . . . . . . . . . . . . . . .
The Importance of Verification . . . . . . . . . . . . . . . . . .
Reconvergence Model . . . . . . . . . . . . . . . . . . . . . . . . .
The Human Factor . . . . . . . . . . . . . . . . . . . . . . . . . . .

1
1
2
4
5

Automation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Poka-Yoke . . . . . . . . . . . . . . . . . . . . . . . ...
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using SystemVerilog
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