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CHAPTER 8

UART

8.1 INTRODUCTION
A universal asynchronous receiver and transmitter (UART) is a circuit that sends parallel
data through a serial line. UARTs are frequently used in conjunction with the EIA (Electronic Industries Alliance) RS-232 standard, which specifies the electrical, mechanical,
functional, and procedural characteristics of two data communication equipment. Because
the voltage level defined in RS-232 is different from that of FPGA I/O, a voltage converter
chip is needed between a serial port and an FPGA’s I/O pins.
The S3 board has an RS-232 port with a standard nine-pin connector. The board contains
the necessary voltage converter chip and configures the various RS-232’s control signals
to automatically generate acknowledgment for the PC’s serial port. A standard straightthrough serial cable can be used to connect the S3 board and PC’s serial port. The S3 board
basically handles the RS-232 standard and we only need to concentrate on design of the
UART circuit.
A UART includes a transmitter and a receiver. The transmitter is essentially a special
shift register that loads data in parallel and then shifts it out bit by bit at a specific rate.
The receiver, on the other hand, shifts in data bit by bit and then reassembles the data. The
serial line is 1 when it is idle. The transmission starts with a start bit, which is 0, followed
by data bits and an optional parity bit, and ends with stop bits, which are 1. The number
of data bits can be 6, 7, or 8. The optional parity bit is used for error detection. For odd
parity, it is set to 0 when the data bits have an odd number of 1’s. For even parity, it is set
to 0 when the data bits have an even number of 1’s. The number of stop bits can be 1, 1.5,
FPGA Prototyping by Verilog Examples. By Pong P. Chu
Copyright c 2008 John Wiley & Sons, Inc.

215

216

UART

idle
start bit
d0

d1

stop bit
d2

Figure 8.1

d3

d4

d5

d6

d7

Transmission of a byte.

or 2. Transmission with 8 data bits, no parity, and 1 stop bit is shown in Figure 8.1. Note
that the LSB of the data word is transmitted first.
No clock information is conveyed through the serial line. Before the transmission starts,
the transmitter and receiver must agree on a set of parameters in advance, which include the
baud rate (i.e., number of bits per second), the number of data bits and stop bits, and use of
the parity bit. The commonly used baud rates are 2400, 4800, 9600, and 19,200 bauds.
We illustrate the design of the receiving and t...
CHAPTER 8
UART
8.1 INTRODUCTION
A universal asynchronous receiver and transmitter (UART) is a circuit that sends parallel
data through a serial line. UARTs are frequently used in conjunction with the EIA (Elec-
tronic Industries Alliance) RS-232 standard, which specifies the electrical, mechanical,
functional, and procedural characteristics of two data communication equipment. Because
the voltage level defined in RS-232 is different from that of FPGA I/O, a voltage converter
chip is needed between a serial port and an FPGAs I/O pins.
The S3board hasan RS-232port witha standardnine-pin connector. The board contains
the necessary voltage converter chip and configures the various RS-232’s control signals
to automatically generate acknowledgment for the PC’s serial port. A standard straight-
through serial cable can be used to connect the S3 board and PC’s serial port. The S3 board
basically handles the RS-232 standard and we only need to concentrate on design of the
UART circuit.
A UART includes a transmitter and a receiver. The transmitter is essentially a special
shift register that loads data in parallel and then shifts it out bit by bit at a specific rate.
The receiver, on the other hand, shifts in data bit by bit and then reassembles the data. The
serial line is 1 when it is idle. The transmission starts with a start bit, which is 0, followed
by data bits and an optional parity bit, and ends with stop bits, which are 1. The number
of data bits can be 6, 7, or 8. The optional parity bit is used for error detection. For odd
parity, it is set to 0 when the data bits have an odd number of 1’s. For even parity, it is set
to 0 when the data bits have an even number of 1’s. The number of stop bits can be 1, 1.5,
FPGA Prototyping by Verilog Examples. By Pong P. Chu
Copyright
c
2008 John Wiley & Sons, Inc.
215
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